-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- Generated by Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
-- Created on Thu Jun 08 12:02:42 2017

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY SM1 IS
    PORT (
        clock : BUFFER STD_LOGIC;
        reset : IN STD_LOGIC := '0';
        EOC : IN STD_LOGIC := '0';
        START : OUT STD_LOGIC;
        OE : OUT STD_LOGIC;
        
        --result0 : BUFFER STD_LOGIC;
        --result1 : BUFFER STD_LOGIC;
        --result2 : BUFFER STD_LOGIC;
        --result3 : BUFFER STD_LOGIC;
        --result4 : BUFFER STD_LOGIC;
        --result5 : BUFFER STD_LOGIC;
        --result6 : BUFFER STD_LOGIC;
        --result7 : BUFFER STD_LOGIC;
        clkinpll: IN STD_LOGIC;
        clkoutpl: buffer STD_LOGIC
    );
END SM1;

ARCHITECTURE BEHAVIOR OF SM1 IS
    TYPE type_fstate IS (state0,state1,state2,state3,state4);
    SIGNAL fstate : type_fstate;
    SIGNAL reg_fstate : type_fstate;
    SIGNAL reg_START : STD_LOGIC := '0';
    SIGNAL reg_OE : STD_LOGIC := '0';
    
COMPONENT pll
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
END COMPONENT;
BEGIN

	clock <= clkoutpl;
    PROCESS (clock,reg_fstate)
    BEGIN
        IF (clock='1' AND clock'event) THEN
            fstate <= reg_fstate;
        END IF;
    END PROCESS;

    PROCESS (fstate,reset,EOC,reg_START,reg_OE)
    BEGIN
        IF (reset='1') THEN
            reg_fstate <= state0;
            reg_START <= '0';
            reg_OE <= '0';
            START <= '0';
            OE <= '0';
        ELSE
            reg_START <= '0';
            reg_OE <= '0';
            START <= '0';
            OE <= '0';
            CASE fstate IS
                WHEN state0 =>
                    reg_fstate <= state1;

                    reg_OE <= '0';

                    reg_START <= '0';
                WHEN state1 =>
                    reg_fstate <= state2;

                    reg_OE <= '0';

                    reg_START <= '1';
                WHEN state2 =>
                    IF ((EOC = '1')) THEN
                        reg_fstate <= state3;
                    ELSE
                        reg_fstate <= state2;
                    END IF;

                    reg_OE <= '0';

                    reg_START <= '0';
                WHEN state3 =>
                    reg_fstate <= state4;

                    reg_OE <= '1';

                    reg_START <= '0';
                WHEN state4 =>
                    reg_fstate <= state0;

                    reg_OE <= '1';

                    reg_START <= '0';
                WHEN OTHERS => 
                    reg_START <= 'X';
                    reg_OE <= 'X';
                    report "Reach undefined state";
            END CASE;
            START <= reg_START;
            OE <= reg_OE;
        END IF;
    END PROCESS;
p1 : pll PORT MAP(areset=>'0',inclk0=>clkinpll,c0=>clkoutpl);    
END BEHAVIOR;
